The invention relates to oscillators for providing a digital train of clock pulses and relates more specifically to NMOS (N-type Metal-Oxide-Semiconductor) technology oscillators in a form suitable for integration with other circuit sections of a larger NMOS integrated digital circuit.
There are a variety of circuits for processing digital electrical signals, such as communications signals, which require a clocking pulse for their operation. Such a clocking pulse is typically generated by an oscillator circuit which includes an inverter amplifier having a fundamental resonance frequency element, such as a quartz crystal, connected in a feedback loop configuration.
Circuits which operate in a charge redistribution or switched-capacitor mode are generally MOS circuits and need for their functioning a clocking pulse provided by an oscillator. It is desirable that this oscillator be integrated as a subcircuit on the same substrate.
Integrated MOS oscillator circuits must be tolerant of the influences of parasitic capacitances and resistances which can affect frequency of the output or even prevent oscillation. Such influences are accentuated with increasing frequency. For oscillators realized with MOS technology, the parasitic capacitance and resistance problem is aggravated by various protective means which may be provided to protect the MOS devices, especially the gates, from spurious voltages arising on the external leads.
A known oscillator circuit generally referred to as a Pierce oscillator can be realized with MOS devices and has a relatively high tolerance to parasitics. However, it also has too low an output amplitude and too variable an offset voltage to permit effective coupling directly to a conventional TTL (transistor-transistor logic) output circuit.